A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of a dual bit flash memory cell consists of an oxide-nitride-oxide (ONO) layer, within which the storage element is contained. The ONO layer is sandwiched between a control gate and a crystalline silicon semiconductor substrate. The substrate includes selectable source/drain regions.
In a dual bit flash memory cell, the flash memory cell stores data by holding charge in the ONO layer. The charge storage element within the ONO layer allows electrons to be stored on either side of the flash memory cell. That is, charge is stored within the ONO layer on either side of the mirror bit memory cell. As a result, the basic memory cell behaves as two independent conventional memory cells. In a typical dual bit flash memory cell, a program operation is done by injecting hot electrons into the ONO layer and an erase operation is done by injecting hot holes into the ONO layer.
A typical configuration of a floating gate flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SiO). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
A typical configuration of an array of dual bit or floating gate flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to source and/or drains.
As the flash memory cells within an array are scaled to higher values, the size of structures within the array are decreased. For example, the bit lines become narrower and narrower within the array of memory cells. However, as the bit lines become narrower, misalignment issues between bit line contacts and the bit lines become more pronounced. As a result, the alignment margin when forming the contact to the bit lines becomes very small, thereby limiting the scaling increase of the array of memory cells.
In addition, in the conventional art, the bit lines can not be silicided, such that, a cobalt silicide (CoSi) layer cannot be formed on the bit lines. The CoSi layer provides for better conductivity, for example between the contact and the bit line. That is, the CoSi layer lowers the bit line contact resistance. However, in conventional manufacturing techniques forming the CoSi layer would electrically couple all the bit lines together in the array of memory cells. In that case, individual cells could not be isolated for reading or programming, since any bit line is coupled to all of the memory cells in the array.
As a remedy for the CoSi short, ONO layers are not removed between the word lines and in the bit line contact regions. As such, when a CoSi layer is deposited for the gates of the memory cells and for the source/drain regions of the periphery, the ONO acts to block CoSi formation between the bit lines of the array of memory cells. However, keeping the ONO layer between the word lines also can induce a leakage current. As a result, a leakage current would cause an entire column of memory cells to malfunction. In particular, with the leakage current, the total current read from a column of memory cells will include the current from the programmed memory cell being read and the leakage current. This may result in the programmed cell appearing to be erased.